Pre-Silicon Validation of Hyper-Threading Technology

Hyper-Threading Technology delivers significantly improved architectural performance at a lower-thantraditional power consumption and die size cost. However, increased logic complexity is one of the trade-offs of this technology. Hyper-Threading Technology exponentially increases the micro-architectural state space, decreases validation controllability, and creates a number of new and interesting micro-architectural boundary conditions. On the Intel Xeon processor family, which implements two logical processors per physical processor, there are multiple, independent logical processor selection points that use several algorithms to determine logical processor selection. Four types of resources: Duplicated, Fully Shared, Entry Tagged, and Partitioned, are used to support the technology. This complexity adds to the presilicon validation challenge. Not only is the architectural state space much larger (see “Hyper-Threading Technology Architecture and Microarchitecture” in this issue of the Intel Technology Journal), but also a temporal factor is involved. Testing an architectural state may not be effective if one logical processor is halted before the other logical processor is halted. The multiple, independent, logical processor selection points and interference from simultaneously executing instructions reduce controllability. This in turn increases the difficulty of setting up precise boundary conditions to test. Supporting four resource types creates new validation conditions such as cross-logical processor corruption of the architectural state. Moreover, HyperThreading Technology provides support for interand intra-logical processor store to load forwarding, greatly increasing the challenge of memory ordering and memory coherency validation.  Intel is a registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.  Xeon is a trademark of Intel Corporation or its subsidiaries in the United States and other countries. This paper describes how Hyper-Threading Technology impacts pre-silicon validation, the new validation challenges created by this technology, and our strategy for pre-silicon validation. Bug data are then presented and used to demonstrate the effectiveness of our pre-silicon Hyper-Threading Technology validation. INTRODUCTION Intel IA-32 processors that feature the Intel NetBurst microarchitecture can also support Hyper-Threading Technology or simultaneous multi-threading (SMT). Presilicon validation of Hyper-Threading Technology was successfully accomplished in parallel with the Pentium 4 processor pre-silicon validation, and it leveraged the Pentium 4 processor pre-silicon validation techniques of Formal Verification (FV), Cluster Test Environments (CTEs), Architecture Validation (AV), and CoverageBased Validation. THE CHALLENGES OF PRE-SILICON HYPER-THREADING TECHNOLOGY VALIDATION The main validation challenge presented by HyperThreading Technology is an increase in complexity that manifested itself in these major ways: • Project management issues • An increase in the number of operating modes: MTmode, ST0-mode, and ST1-mode, each described in “Hyper-Threading Technology Architecture and Microarchitecture” in this issue of the Intel Technology Journal.  Intel and Pentium are registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.  NetBurst is a trademark of Intel Corporation or its subsidiaries in the United States and other countries. Intel Technology Journal Q1, 2002. Vol. 6 Issue 1. Pre-Silicon Validation of Hyper-Threading Technology 2 • Hyper-Threading Technology squared the architectural state space. • A decrease in controllability. • An increase in the number and complexity of microarchitectural boundary conditions. • New validation concerns for logical processor starvation and fairness. Microprocessor validation already was an exercise in the intractable engineering problem of ensuring the correct functionality of an immensely complex design with a limited budget and on a tight schedule. Hyper-Threading Technology made it even more intractable. HyperThreading Technology did not demand entirely new validation methods and it did fit within the already planned Pentium 4 processor validation framework of formal verification, cluster testing, architectural validation, and coverage-based microarchitectural validation. What Hyper-Threading Technology did require, however, was an increase in validation staffing and a significant increase in computing capacity.